A 256K CMOS SRAM with variable impedance data-line loads
- 1 October 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 20 (5) , 924-928
- https://doi.org/10.1109/jssc.1985.1052416
Abstract
A 256K (32K/spl times/8) CMOS SRAM utilizing variable impedance loads and a pulsed word-line (PWL) technique is described. In the WRITE cycle, the variable impedance loads of the data lines enter a high impedance state and reduce the operating power. During the READ cycle, the PWL technique is used to achieve high-speed operation and low power dissipation. The internal clocks generated by the address transition detectors activate word-line and sense amplifiers for READ operation and disable them after the data are sent to D/SUB out/ buffers. This PWL technique eliminates the precharge time of 20 ns, which corresponds to 30% of the access time. The RAM offers 45-ns address access time and 40-mW operating power in the WRITE cycle of 1 MHz.Keywords
This publication has 5 references indexed in Scilit:
- A low power 46 ns 256 kbit CMOS static RAM with dynamic double word lineIEEE Journal of Solid-State Circuits, 1984
- A 20ns 64K CMOS SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A 64Kb CMOS RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- A fault-tolerant 30 ns/375 mW 16Kx1 NMOS static RAMIEEE Journal of Solid-State Circuits, 1981
- A high-speed, low-power Hi-CMOS 4K static RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978