A 10-/spl mu/W standby power 256K CMOS SRAM
- 1 October 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 20 (5) , 935-940
- https://doi.org/10.1109/jssc.1985.1052418
Abstract
A 32K/spl times/8-bit CMOS static RAM using titanium polycide technology has been developed. The RAM has a standby power of 10 /spl mu/W, an active power of 175 mW, and an access time of 55 ns. The standby power has been achieved by an optimization of polysilicon resistors in a memory cell. A digit line circuit controlled by three internal clocks contributes to reduction of active power. The cell size has been reduced to 89.5 /spl mu/m/SUP 2/ by using both a buried isolation and a polycide GND line. Furthermore a simplified address-transition detection circuit and a single data bus configuration result in a small layout area, thus offering a 40.7 mm/SUP 2/ die size.Keywords
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