An ultralow power 8Kx8-bit full CMOS RAM with a six-transistor cell
- 1 October 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 17 (5) , 798-803
- https://doi.org/10.1109/jssc.1982.1051821
Abstract
A fully static 8K word by 8 bit CMOS RAM, with a six-transistor CMOS cell structure to achieve an extremely low standby power of less than 50 nW has been developed. A 2 /spl mu/m, double polysilicon CMOS process was utilized to realize a 19/spl times/22 /spl mu/m cell size. Redundance technology with polysilicon laser fuses was also developed for improving fabrication yield with relatively large chip size, i.e. 5.92/spl times/7.49 mm. In addition, for reducing operational power dissipation while maintaining fully static operation from outside on the chip, an internally clocked low-power circuit technology using row address transition detectors was employed, which results in only 15 mW operational power at 1 MHz by cutting off all DC current paths. The RAM offers an 80 ns address access time.Keywords
This publication has 8 references indexed in Scilit:
- A HI-CMOSII 8K × 8b static RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- A 64Kb CMOS RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- A 15nW standby power 64Kb CMOS RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- Redundancy techniques for fast static RAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- A 25ns 16 × 1 static RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- 2K × 8 bit Hi-CMOS static RAM'sIEEE Transactions on Electron Devices, 1980
- A 2Kx8-bit static MOS RAM with a new memory cell structureIEEE Journal of Solid-State Circuits, 1980
- Fully static 16Kb bulk CMOS RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1980