VLSI implementation of a 100 MHz pipelined ADPCM codec chip
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- Roundoff error analysis of the pipelined ADPCM coderPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A high-speed architecture for ADPCM codecPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A pipelined adaptive lattice filter architectureIEEE Transactions on Signal Processing, 1993
- High-speed VLSI arithmetic processor architectures using hybrid number representationJournal of Signal Processing Systems, 1992
- Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decompositionIEEE Transactions on Acoustics, Speech, and Signal Processing, 1989
- High-speed CMOS circuit techniqueIEEE Journal of Solid-State Circuits, 1989
- A single-chip adaptive DPCM video codecIEEE Journal of Solid-State Circuits, 1989
- Parallel bit-level pipelined VLSI designs for high-speed signal processingProceedings of the IEEE, 1987
- Design of a DPCM codec for VLSI realization in CMOS technologyProceedings of the IEEE, 1985
- Optimizing Synchronous Circuitry by Retiming (Preliminary Version)Published by Springer Nature ,1983