The ATM shuffleout switching fabric: Design and implementation issues

Abstract
This paper describes the design and implementation aspects of the Shuffleout switch, a new class of switching fabric architectures. The key points of this structure are the adoption of a memoryless multistage interconnection network and a new packet routing strategy. Compared to the basic multistage shuffle interconnection network of Shuffleout, adopting 2×4 switching elements, three other architectures of the interconnection network are described, which use larger switching elements, that is 4×6, 3×5 and 4×8. Adopting these upgraded structures aims not only at decreasing the number of interconnection network stages that provide a given cell loss probability, thus reducing the switching fabric complexity, but also at improving fairness in the network. The VLSI hardware design of a switching element and of a chip is then described with reference to the basic Shuffleout structure, with design and implementation details on their major functional blocks. Finally a complexity comparison of the different enhanced architectures is assessed.

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