Parameterized SPICE subcircuits for submicron multilevel interconnect modeling
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A parameterized interconnect modeling system which provides VLSI designers with a direct link between finite-difference 2-D/3-D capacitance simulators and SPICE simulators is described. In this way, both the device modeling and the interconnect modeling are parameterized, and the time needed to generate SPICE inputs is estimated to decrease by two or three orders of magnitude with this approach.Keywords
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