Process integration for 64 M DRAM using an asymmetrical stacked trench capacitor (AST) cell
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 647-650
- https://doi.org/10.1109/iedm.1990.237116
Abstract
The key points of sub-half-micron CMOS technologies for 64-Mb DRAM fabrication are described. The main features of the technologies are (1) an asymmetrical stacked trench capacitor (AST) cell, (2) localized channel implantation through the field oxide (LIF), and (3) a 0.4- mu m transistor with LDD (lightly doped drain) n/sup -/ impurity of arsenic. The lithographic levels are 0.4 mu m for critical layers. achieved using a KrF excimer laser stepper. The AST cell has a stacked capacitor in a trench; the trenches are located asymmetrically with respect to each other. A small cell area of 1.53 mu m/sup 2/ has been achieved by adopting the LIF isolation and the As LDD transistor for the AST cell. An experimental 64-Mb DRAM chip has been successfully fabricated using these technologies.<>Keywords
This publication has 1 reference indexed in Scilit:
- A corrugated capacitor cell (CCC) for megabit dynamic MOS memoriesIEEE Electron Device Letters, 1983