DLS: A scheduling algorithm for high-level synthesis in VHDL
- 30 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 393-397
- https://doi.org/10.1109/edac.1993.386444
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- Percolation based synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Synthesis using path-based scheduling: algorithms and exercisesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- ASIC design using the high-level synthesis system CALLAS: a case studyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Path-based scheduling for synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- Trace Scheduling: A Technique for Global Microcode CompactionIEEE Transactions on Computers, 1981