An analytical back-gate bias effect model for ultrathin SOI CMOS devices
- 1 April 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 40 (4) , 755-765
- https://doi.org/10.1109/16.202788
Abstract
An analytical back-gate bias effect model for ultrathin SOI CMOS devices is presented. As verified by PISCES results, the analytical SOI CMOS back-gate bias effect model provides a much better accuracy in the integral potential distribution and the threshold voltage as the back-gate bias is changedKeywords
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