Hierarchical timing view generation including accurate modeling for false paths
- 1 January 1989
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 13.3/1-13.3/4
- https://doi.org/10.1109/cicc.1989.56747
Abstract
A hierarchical method for efficient solving the false path problem is presented. In a preprocessing step, all the local and user-intended logical incompatibilities are eliminated by generating timing views for these basic cells. These timing views are hierarchically composed, and there remain fewer (or no) logical incompatibilities. Therefore, the CPU-times required by the longest sensitizable path algorithm are much lower, and, for complex examples, this can mean a reduction of two orders of magnitudeKeywords
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