Transient and Total Dose Radiation Properties of the CMOS/SOS EPIC Chip Set

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Abstract
This paper addresses the measurements of threshold upset dose rates and total dose properties of devices in the EPIC (Emulation and Programmable Integrated Circuits) chip set. These consisted of the Gate Universal Array (GUA, TA11093), General Processor Unit (GPU, GPOO1), 4K Memory (TCS146), 8K ROM (TA11256), Multiplier (GP503), and Level Shifter (GP511). All of these CMOS/SOS device types were fabricated with a rad-hard process in a study of 21 lots which was performed to determine reproducibility of total dose hardness. The transient measurements were made on a Linac using a 20 nanosecond electron pulse of 15 or 40 MeV energies. Measurements of the upset rate and dose/pulse required to cause temporary functional failure of the GPU device were also made using a 2.1 microsecond pulse width. Bias dependence of upset rate and impact on dose rate of using total dose irradiated parts were also investigated. Results showed that upset rates decreased both for lower bias voltage and for total dose degraded parts. Upset rates for stored data varied from a low of 4.5 × 1010 to a high of 4.1 × 1011 rads (Si)/second for previously unirradiated parts. Reproducibility of hardness is illustrated by the average values and standard deviations for leakage currents, dynamic currents, speed, and fuctionality versus dose of representative device types in this family of parts.

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