A 64Kx1 bit dynamic ED-MOS RAM
- 1 October 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 13 (5) , 600-606
- https://doi.org/10.1109/jssc.1978.1051106
Abstract
A 64K/spl times/1 bit dynamic RAM based on an innovative short channel ED-MOS process technology and an improved ED-MOS sense amplifier circuit has been realized. The RAM has been designed by using 2-3 /spl mu/m design rules and employing ED-MOS peripheral circuits capable of low supply voltage operation. As a result, dynamic memory operation has been demonstrated with an access time less than 140 ns and a cycle time of 350 ns, using a single 5 V power supply.Keywords
This publication has 4 references indexed in Scilit:
- Double boron implant short-channel MOSFETIEEE Transactions on Electron Devices, 1977
- A 16 384-bit dynamic RAMIEEE Journal of Solid-State Circuits, 1976
- Fabrication of a miniature 8K-bit memory chip using electron-beam exposureJournal of Vacuum Science and Technology, 1975
- An analysis of the threshold voltage for short-channel IGFET'sSolid-State Electronics, 1973