A high throughput FPGA implementation of a bit-level matrix product
- 7 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 356-364
- https://doi.org/10.1109/sips.2000.886734
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- A re-evaluation of the practicality of floating-point operations on FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- High throughput VLSI implementation of discrete orthogonal transforms using bit-level vector-matrix multiplierIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1999
- The use of data dependence graphs in the design of bit-level systolic arraysIEEE Transactions on Acoustics, Speech, and Signal Processing, 1990
- Systolic architectures for the computation of the discrete Hartley and the discrete cosine transforms based on prime factor decompositionIEEE Transactions on Computers, 1990
- A VLSI chip for the winograd/Prime factor algorithm to compute the discrete Fourier transformIEEE Transactions on Acoustics, Speech, and Signal Processing, 1986
- The design of bit parallel systolic algorithms for matrix-vector and matrix-matrix multiplicationPublished by Association for Computing Machinery (ACM) ,1985
- A Two's Complement Parallel Array Multiplication AlgorithmIEEE Transactions on Computers, 1973