A 1 Gb DRAM for file applications

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Abstract
A number of large capacity DRAMs have been developed recently for file applications because data storage devices play an important role in high-speed communication and graphic systems. Such file memories must have low power dissipation, high data transfer rate and low cost. A low chip-yield problem is reported to occur in the manufacture of large capacity DRAMs. To address both device requirements and yield limitations, new circuit technologies have been developed for 1 Gb DRAMs. By implementing a time-shared offset cancel sensing scheme and adopting a diagonal bit-line (DBL) cell, the chip size is reduced to 70% of that of a conventional DRAM. A defective word-line Hi-Z standby scheme and a flexible multi-macro architecture produces about twice the yield as that resulting from conventional architecture. 32 b I/Os with a pipeline circuit technique realizes a 400 MB/s data transfer rate. A 1 Gb DRAM with these features uses 0.25 /spl mu/m CMOS.

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