Efficient timing constraint derivation for optimally retiming high speed processing units
- 17 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1, 48-53
- https://doi.org/10.1109/ishls.1994.302342
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- PHIDEO: a silicon compiler for high speed algorithmsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Retiming synchronous circuitryAlgorithmica, 1991
- Flexible datapath compilation for PhideoPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- Chapter IV Network flowsPublished by Elsevier ,1989