Self-timed logic using current-sensing completion detection (CSCD)
- 10 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 187-191
- https://doi.org/10.1109/iccd.1991.139878
Abstract
A completion-detection method is proposed for efficiently implementing Boolean functions as self-timed logic structures. Current-sensing completion detection (CSCD) allows self-timed circuits to be designed using single-rail variable encoding (one signal wire per logic variable) and implemented in about the same silicon area as an equivalent synchronous implementation. Compared to dual-rail encoding methods, CSCD can reduce the number of signal wires and transistors used by approximately 50%. CSCD implementations improved performance over equivalent dual-rail designs because of: reduced parasitic capacitance, removal of spacer tokens in the data stream, and computation state similarity of consecutive data variables. Several CSCD configurations are described and evaluated and transistor-level implementations are provided for comparison.Keywords
This publication has 2 references indexed in Scilit:
- MicropipelinesCommunications of the ACM, 1989
- A self-testing ALU using built-in current sensingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989