A simple, high-precision, high speed digital frequency multiplier

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Abstract
The design of a digital frequency multiplier based on mod-N arithmetic, where N is the multiplying factor, is presented. For N<2/sup n/, n a positive integer, the correction circuit requires a single binary adder and operates on (n+1) bits, maintaining a zero-mean output frequency error. For practical values of N, the correction scheme requires 3 master clock periods, with a minimum clock period equivalent to 6 unit gate delays. Hence, for N/spl ges/3, the lower limit on the master clock frequency is only N times the maximum input frequency. For applications where the maximum input frequency is less or equal to N/sup 2/ times the master clock frequency, a solution requiring no arithmetic element is proposed. Field-programmable gate array implementations are described and a detailed frequency error analysis is presented.

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