Fault models and tests for two-port memories
- 27 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Dual port static RAM testingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- March LR: a test for realistic linked faultsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Testing complex couplings in multiport memoriesIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995
- Serial interfacing for embedded-memory testingIEEE Design & Test of Computers, 1990