The influence of emitter efficiency on single transistor latch in silicon-on-insulator MOSFETs

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 141-142
https://doi.org/10.1109/sossoi.1990.145751

Abstract

It is demonstrated that a significant improvement in the breakdown voltage of an SOI (silicon-on-insulator) MOSFET can be achieved by stress-induced damage to the source/body junction. The damage serves to degrade the injection efficiency of this junction and thus suppresses the parasitic lateral bipolar associated with source/body/drain. The experiment indicates the usefulness of source engineering to the latch problem.<>

Keywords

MOSFETS
SILICON ON INSULATOR TECHNOLOGY
LATCHES
DEGRADATION
STRESS
VOLTAGE
IMPLANTS
ARGON
ANNEALING
THICKNESS MEASUREMENT

This publication has 1 reference indexed in Scilit:

Interpretation of capacitance-voltage characteristics on silicon-on-insulator (SOI) capacitors
Solid-State Electronics, 1989