A Method of Theoretical Analysis of High-Speed Junction Diode Logic Circuits

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Abstract
The charge storage (and, consequently, the recovery time) problem of a p-n junction diode has been a most troublesome phenomenon in the application of junction diodes in switching circuits. If many diodes in a logic gate are switched simultaneously from conduction to cutoff, large sums of stored charge will be generated and will tend to reverse the state of the nonswitching diodes in the same circuit. Accordingly, a possible false logic response may result. Unfortunately, the diode models presently available are useless for analyzing such transients. For this reason, a new diode model has been devised. From a study of the physical process in a junction diode, a unique relationship can be established between the terminal electric properties and the charge storage in the base material, of the diode. The relationship can be shown in a simple flowgraph. From this flowgraph a lumped charge model of a p-n junction diode is proposed. Utilizing this model, one can simply and uniquely solve the transient problems encountered in diode switching circuits, while only two parameters, the saturation current Is, and the diode time constant Td, are required to evaluate the solution numerically.