A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications
- 1 February 2007
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01936530,p. 440-614
- https://doi.org/10.1109/isscc.2007.373483
Abstract
A power-efficient 6.25Gb/s transceiver in 90nm CMOS for chip-to-chip communication is presented, it dissipates 2.2mW/Gb/s operating at a BER of -15 over a channel with -15dB attenuation at 3.125GHz. A shared LC-PLL, resonant clock distribution, a low-swing voltage-mode transmitter, a low-power phase rotator, and a software-based CDR and an adaptive equalizer are used to reduce powerKeywords
This publication has 3 references indexed in Scilit:
- A 0.6 to 9.6Gb/s binary backplane transceiver core in 0.13μm CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A 27-mW 3.6-Gb/s I/O TransceiverIEEE Journal of Solid-State Circuits, 2004
- Improved switched tuning of differential CMOS VCOsIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2002