A 0.6 to 9.6Gb/s binary backplane transceiver core in 0.13μm CMOS
- 30 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01936530,p. 64-66
- https://doi.org/10.1109/isscc.2005.1493870
Abstract
A backplane transceiver core in 0.13 /spl mu/m dual-gate CMOS, operating at 0.6 to 9.6 Gb/s with an area of 0.56 mm/sup 2/ and dissipating 150 mW at 6.25 Gb/s, is presented. This core uses a unique adaptive receive equalization strategy, transmit pre-emphasis, and has extensive optional test features including a built-in BER tester and an on-chip receiver sampling scope.Keywords
This publication has 2 references indexed in Scilit:
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- Adaptive equalizationIEEE Communications Magazine, 1982