A Critical Path Delay Check System
- 1 January 1981
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 118-123
- https://doi.org/10.1109/dac.1981.1585341
Abstract
A Critical Path Delay Check System for designing computers is described. It calculates the critical path delay between the start and end points. It can be used in the early stage of design when, for example, the location of the components on a plug-in card has not yet been determined. Some algorithms for predicting delays are also introduced.Keywords
This publication has 2 references indexed in Scilit:
- Logic Verification System for Very Large Computers Using LSI'sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- Design Verification and Performance AnalysisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978