GaAs MESFET differential pass-transistor logic
- 13 September 1990
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 26 (19) , 1597-1598
- https://doi.org/10.1049/el:19901023
Abstract
A GaAs MESFET implementation of differential pass-transistor logic (DPTL) is presented. This logic technique combines the greater area efficiencies and high operation speeds of ratioless, pass-transistor circuits with the additional advantages of good noise immunity and low power dissipation. Experimental results are provided for a four-bit counter implemented in a 1 =m, depletion (D)-mode MESFET technology to demonstrate both the functionality and noise immunity of GaAs DPTL.Keywords
This publication has 2 references indexed in Scilit:
- Optimization of Submicron CMOS Differential Pass-Transistor LogicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- A 3.8 ns CMOS 16×16 multiplier using complementary pass transistor logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989