Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip

1 January 2007

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 1-8
https://doi.org/10.1109/test.2007.4437561

Abstract

The Niagara2 System-on-Chip is SUN Microsystem's latest processor in the Eco-sensitive CoolThreads line of multi-threaded servers. This DFT survey of the Niagara2 chip introduces the RAWWCas memory test, a Hybrid Flop Design and a fast efficient bitmapping architecture called DMO. It also showcases some excellent DFT results for this challenging system-on-chip design project.

Keywords

DESIGN FOR TESTABILITY
SUN
TESTING
MANUFACTURING
SYSTEM-ON-A-CHIP
CLOCKS
RANDOM ACCESS MEMORY
NETWORK-ON-A-CHIP
REGISTERS
SCATTERING

This publication has 1 reference indexed in Scilit:

DFT advances in the Motorola's MPC7400, a PowerPC/sup TM/ G4 microprocessor
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003