High-level delay estimation for technology-independent logic equations
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- ATV: an abstract timing verifierPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Timing optimization of combinational logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987