A 4b × 4b multiplier and 3b counter in Josephson threshold logic

1 January 1986

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXIX, 196-197

Abstract

This Paper will report on the development of a 4×4b parallel multiplier with a carry-to-carry delay time of 279ps and a 3b binary counter operating at 2.2 GHz implemented in Josephson junction technology.

Keywords

COUNTING CIRCUITS
JOSEPHSON JUNCTIONS
LARGE SCALE INTEGRATION
MAGNETIC CIRCUITS
ADDERS
POWER AMPLIFIERS
DC GENERATORS
POWER GENERATION
CURRENT MEASUREMENT
VOLTAGE

This publication has 4 references indexed in Scilit:

An integration of all refractory Josephson logic LSI circuit
IEEE Transactions on Magnetics, 1985
A DC-powered Josephson flip-flop
IEEE Transactions on Magnetics, 1979
A Josephson tunnelling logic adder
IEEE Transactions on Magnetics, 1974
An integrated threshold gate
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1967