Negative dynamic resistance in MOS devices
- 1 June 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 13 (3) , 378-380
- https://doi.org/10.1109/jssc.1978.1051060
Abstract
No abstract availableKeywords
This publication has 1 reference indexed in Scilit:
- A computer-aided design model for high-voltage double diffused MOS (DMOS) transistorsIEEE Journal of Solid-State Circuits, 1976