A 1.4 GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture
- 7 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 204-205,
- https://doi.org/10.1109/isscc.2000.839750
Abstract
No abstract availableThis publication has 5 references indexed in Scilit:
- A fully integrated CMOS DCS-1800 frequency synthesizerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A low-noise 1.6-GHz CMOS PLL with on-chip loop filterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Future directions in silicon ICs for RF personal communicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applicationsIEEE Journal of Solid-State Circuits, 1997