A high-speed ESFI SOS programmable logic array with an MNOS version
- 1 October 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 10 (5) , 331-336
- https://doi.org/10.1109/jssc.1975.1050619
Abstract
A programmable logic array (PLA) with J-K flip-flops as feedback loops and having a maximum operating speed of 12 MHz has been designed and realized in epitaxial-silicon-films-on-insulators (ESFI) silicon-on-sapphire (SOS) technology. The advantages of the ESFI SOS technology and the circuit of the PLA are described and experimental results are presented. In addition, a twin PLA using metal-nitride-oxide-semiconductor (MNOS) transistors in the AND and OR matrices and having the same number of inputs, outputs, and feedback loops as the mask-programmable PLA has been designed. This MNOS PLA has full on-chip decoding capability and can be programmed or reprogrammed individually. The circuit of the MNOS PLA is described and the speed of the device is calculated.Keywords
This publication has 2 references indexed in Scilit:
- Fully decoded MNOS storage arrays in ESFI MOS technologyIEEE Journal of Solid-State Circuits, 1974
- Grounded load complementary FET circuits: Sceptre analysisIEEE Journal of Solid-State Circuits, 1973