A 256K bit dynamic RAM
- 1 October 1980
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 15 (5) , 872-874
- https://doi.org/10.1109/jssc.1980.1051485
Abstract
A 256K/spl times/1 bit NMOS dynamic RAM, fabricated using conventional n-channel two-layer polysilicon gate technology, is described. The memory cell was laid out in 5.7 /spl mu/m/spl times/12.5 /spl mu/m, and the die measured 4.84 mm/spl times/8.59 mm which can use a standard 300 mil 16 pin DIP. Reduction of the bit line capacitance was accomplished using the second polysilicon layer for the bit line. Through the use of large memory cell capacitance and special device coating techniques, alpha particle immunity was increased. The memory offers a 160 ns typical access time, 350 ns cycle time, and 250 mW active power dissipation.Keywords
This publication has 2 references indexed in Scilit:
- A fault-tolerant 64K dynamic RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- Single transistor MOS RAM using a short-channel MOS transistorIEEE Journal of Solid-State Circuits, 1978