Dynamic analysis of 3 stage Dickson voltage multiplier for an optimized design
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
In this paper we develop dynamic models for an ideal 3 stage Dickson voltage multiplier. Starting from the model proposed, an optimized design can be performed. The circuit discussed is used in a power IC or memory to allow the switching on of an MOS device. The models proposed are validated both by measurement on breadboard and by Spice simulation.Keywords
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