Trace processors
Top Cited Papers
- 22 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10724451,p. 138-148
- https://doi.org/10.1109/micro.1997.645805
Abstract
Traces are dynamic instruction sequences constructed and cached by hardware. A microarchitecture organized around traces is presented as a means for efficiently executing many instructions per cycle. Trace processors exploit both control flow and data flow hierarchy to overcome complexity and architectural limitations of conventional superscalar processors by (1) distributing execution resources based on trace boundaries and (2) applying control and data prediction at the trace level rather than individual branches or instructions. Three sets of experiments using the SPECInt95 benchmarks are presented. (i) A detailed evaluation of trace processor configurations: the results affirm that significant instruction-level parallelism can be exploited in integer programs (2 to 6 instructions per cycle). We also isolate the impact of distributed resources, and quantify the value of successively doubling the number of distributed elements. (ii) A trace processor with data prediction applied to inter-trace dependences: potential performance improvement with perfect prediction is around 45% for all benchmarks. With realistic prediction, gcc achieves an actual improvement of 10%. (iii) Evaluation of aggressive control flow: some benchmarks benefit from control independence by as much as 10%.Keywords
This publication has 12 references indexed in Scilit:
- Limits of Control Flow on ParallelismPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Increasing the instruction fetch rate via block-structured instruction set architecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- The performance potential of data dependence speculation and collapsingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Assigning confidence to conditional branch predictionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Path-based next trace predictionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Control flow speculation in multiscalar processorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- The predictability of data valuesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- ARB: a hardware mechanism for dynamic reordering of memory referencesIEEE Transactions on Computers, 1996
- Multiscalar processorsPublished by Association for Computing Machinery (ACM) ,1995
- Hardware Support For Large Atomic Units in Dynamically Scheduled MachinesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988