Increasing the instruction fetch rate via block-structured instruction set architectures

This publication has 21 references indexed in Scilit:

• Trace cache: a low latency approach to high bandwidth instruction fetching
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Multiple-block ahead branch predictors
  Published by Association for Computing Machinery (ACM) ,1996
• Enhancing instruction scheduling with a block-structured ISA
  International Journal of Parallel Programming, 1995
• Increasing the instruction fetch rate via multiple branch prediction and a branch address cache
  Published by Association for Computing Machinery (ACM) ,1993
• The superblock: An effective technique for VLIW and superscalar compilation
  The Journal of Supercomputing, 1993
• An efficient resource-constrained global scheduling technique for superscalar and VLIW processors
  ACM SIGMICRO Newsletter, 1992
• Two-level adaptive training branch prediction
  Published by Association for Computing Machinery (ACM) ,1991
• Highly concurrent scalar processing
  ACM SIGARCH Computer Architecture News, 1986
• HPS, a new microarchitecture: rationale and introduction
  Published by Association for Computing Machinery (ACM) ,1985
• Efficient hardware for multiway jumps and pre-fetches
  Published by Association for Computing Machinery (ACM) ,1985