Architecture synthesis of high-performance application-specific processors
Open Access
- 4 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- Organization Of Array Data For Concurrent Memory AccessPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- The White Dwarf: a high-performance application-specific processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Automatic synthesis of a multi-bus architecture for DSPPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Architecture synthesis of high-performance application-specific processorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Force-directed scheduling for the behavioral synthesis of ASICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- A global resource-constrained parallelization techniquePublished by Association for Computing Machinery (ACM) ,1989
- A VLIW architecture for a trace scheduling compilerIEEE Transactions on Computers, 1988
- Adaptive mesh refinement in the finite element computation of magnetic fieldsIEEE Transactions on Magnetics, 1985
- Interpolated finite impulse response filtersIEEE Transactions on Acoustics, Speech, and Signal Processing, 1984
- Very Long Instruction Word architectures and the ELI-512Published by Association for Computing Machinery (ACM) ,1983