Suppression of latch in SOI MOSFETs by silicidation of source
- 23 May 1991
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 27 (11) , 1003-1005
- https://doi.org/10.1049/el:19910625
Abstract
It is demonstrated that silicidation of the source region in a silicon-on-insulator MOSFET can improve the parasitic bipolar induced breakdown voltage to beyond 5 V. The technique results in a degradation of the parasitic bipolar current gain by increasing the minority carrier current across the source body junction, thereby causing a reduction in the emitter efficiency. Silicidation of both the source and drain regions is performed simultaneously thus maintaining device symmetry and simplicity of processing. No significant degradation of drain leakage leakage current was observed.Keywords
This publication has 2 references indexed in Scilit:
- The influence of emitter efficiency on single transistor latch in silicon-on-insulator MOSFETsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A simple model to predict the holding voltage for SOI MOSFETs operating in the latch statePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002