A 1 mu A retention 4 Mb SRAM with a thin-film-transistor load cell
- 1 January 1990
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A 1- mu A-retention, 4-Mb SRAM with a thin-film-transistor (TFT) load cell, fabricated in a 0.5- mu m triple-poly-Si (first- and third-level W-polycide) double-Al CMOS technology is described. A 200-fA/b retention current is achieved. utilizing the PMOS-type TFT, in which the n/sup +/ diffusion area of the driver transistor acts as a gate electrode of the TFT. The RAM, which has a built-in voltage down converter (VDC), operates with a 3.3-V supply from a standard 5 V+or-10% external supply. In the battery backup mode, an on-chip external-supply-level sensor disables the VDC, and the retention current of the RAM is reduced to 1 mu A.<>Keywords
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