An Improvement of Reliability of Memory System with Skewing Reconfiguration
- 1 October 1981
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-30 (10) , 811-812
- https://doi.org/10.1109/TC.1981.1675699
Abstract
In a memory system with skewing reconfiguration, a virtual memory address is encoded by an address encoder to avoid using a faulty memory area. This correspondence shows one method to improve the reliability of the address encoder by encoding a virtual memory address together with data to an error correcting code. Only a few additional gates are required for the implementation if the memory system has already employed an error correcting code.Keywords
This publication has 2 references indexed in Scilit:
- Orthogonal Latin Square Configuration for LSI Memory Yield and Reliability EnhancementIEEE Transactions on Computers, 1975
- An Organization for a Highly Survivable MemoryIEEE Transactions on Computers, 1974