Combining System Level Modeling with Assertion Based Verification
- 31 March 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 310-315
- https://doi.org/10.1109/isqed.2005.32
Abstract
Assertion based verification (ABV) using the PSL language is currently gaining acceptance as an essential method for functional verification of hardware. A basic technique to implement ABV is to embed temporal assertions in RTL code. The paper describes the use of a PSL-based ABV methodology in a C++-based system level modeling and simulation environment. We describe the considerations of porting a tool, which translates PSL to VHDL/Verilog, to support C++, a language which was designed for software and does not have concurrent language constructs. The translation scheme is shown to be adaptable to all C-based environments. We exemplify the wide applicability of this scheme by detailing its successful deployment in a SystemC-based industrial system-on-chip (SoC) project.Keywords
This publication has 1 reference indexed in Scilit:
- A methodology for the verification of a "system on chip"Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003