Silicon stacked tunnel transistor for high-speedand high-density random access memory gain cells

13 May 1999

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 35 (10) , 848-850
https://doi.org/10.1049/el:19990574

Abstract

Novel stacked tunnel transistors have been fabricated on silicon dioxide using a standard 0.2 µm silicon process. From the measured characteristics it is shown that random access memory operations with 10 ns read/write times are possible in cells which occupy the area of just one transistor.

Keywords

STANDARD SI PROCESS
HIGH-DENSITY RAM GAIN CELLS
SI-SIO2
HIGH-SPEED RAM GAIN CELLS
RANDOM ACCESS MEMORY GAIN CELLS
10 NS
SI STACKED TUNNEL TRANSISTOR
0.2 MICRON

This publication has 2 references indexed in Scilit:

Scaling theory for double-gate SOI MOSFET's
IEEE Transactions on Electron Devices, 1993
Thermal nitridation of Si and SiO₂for VLSI
IEEE Transactions on Electron Devices, 1985