Optimum stacked layout for analog CMOS ICs
- 30 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A rigorous and efficient technique is presented for module generation in a maximally stacked layout paradigm for CMOS analog integrated circuits. Analog constraints on symmetry and matching provide a key for heuris- tics substantially reducing the computational complexity of robust graph algorithms. The solution found minimizes a cost function accounting for parasitic control and routability considerations. Combin ed with sensitiv- ity analysis and automatic constraint generation, this alg orithm provides a suitable performance-driven approach to analog layout module generation. Examples are reported showing the effectiveness of our approach.Keywords
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