Optimal Chaining of CMOS Transistors in a Functional Cell
- 1 September 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 6 (5) , 795-801
- https://doi.org/10.1109/tcad.1987.1270322
Abstract
We describe an algorithm that maps a CMOS circuit diagram into an area-efficient, high-performance layout in the style of a transistor chain. It is superior to other published algorithms of this kind in terms of the class of input circuits it accepts, its efficiency, and the quality of the results it produces. This algorithm is intended for the automatic generation of basic cells in a custom or semicustom design environment, thereby removing the burden of arduous mask definition from the designer. We show how our method was used to compose cells in a row into a functional slice (e.g. an adder) that can be used in, say, a data path.Keywords
This publication has 7 references indexed in Scilit:
- An automatic cell pattern generation system for CMOS transistor-pair array LSIIntegration, 1986
- Linear algorithms for two CMOS layout problemsPublished by Springer Nature ,1986
- PSI: A symbolic layout systemIBM Journal of Research and Development, 1984
- An Algorithm to Compact a VLSI Symbolic Layout with Mixed ConstraintsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- A “greedy” channel routerPublished by Association for Computing Machinery (ACM) ,1982
- Optimal Layout of CMOS Functional ArraysIEEE Transactions on Computers, 1981
- Algorithm 457: finding all cliques of an undirected graphCommunications of the ACM, 1973