Bit-Level systolic architectures for high performance IIR filtering
- 1 August 1989
- journal article
- Published by Springer Nature in Journal of Signal Processing Systems
- Vol. 1 (1) , 9-24
- https://doi.org/10.1007/bf00932062
Abstract
No abstract availableKeywords
This publication has 14 references indexed in Scilit:
- Bit-level systolic arrays for IIR filteringPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Systolic building block for high performance recursive filteringPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Systolic IIR filters with bit level pipeliningPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Application-specific CAD of VLSI second-order sectionsIEEE Transactions on Acoustics, Speech, and Signal Processing, 1988
- Concurrent cellular VLSI adaptive filter architecturesIEEE Transactions on Circuits and Systems, 1987
- Some Systolic Array Developments in the United KingdomComputer, 1987
- High-speed recursive digital filter realizationCircuits, Systems, and Signal Processing, 1984
- Fault-Tolerant VLSI Systolic Arrays and Two-Level PipeliningPublished by SPIE-Intl Soc Optical Eng ,1983
- An approach to the implementation of digital filtersIEEE Transactions on Audio and Electroacoustics, 1968
- Signed-Digit Numbe Representations for Fast Parallel ArithmeticIEEE Transactions on Electronic Computers, 1961