A formal approach to mpsoc performance verification
- 8 April 2003
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Computer
- Vol. 36 (4) , 60-67
- https://doi.org/10.1109/mc.2003.1193230
Abstract
Multiprocessor system on chip designs use complex on-chip networks to integrate different programmable processor cores, specialized memories, and other components on a single chip. MpSoC have been become the architecture of choice in many industries. Their heterogeneity inevitably increases with intellectual-property integration and component specialization. System integration is becoming a major challenge in their design. Simulation is state of the art in MpSoC performance verification, but it has conceptual disadvantages that become disabling as complexity increases. Formal approaches offer a systematic alternative. The article presents a technology that uses event model interfaces and a novel event flow mechanism that extends formal analysis approaches from real-time system design into the multiprocessor system on chip domain.Keywords
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