Layout methods to reduce CMOS stuck-open faults and enhance testability
- 1 January 1987
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Test Generation for MOS Circuits Using D-AlgorithmPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Design for testability—A surveyProceedings of the IEEE, 1983
- Fault Coverage in Digital Integrated CircuitsBell System Technical Journal, 1978
- Fault Modeling and Logic Simulation of CMOS and MOS Integrated CircuitsBell System Technical Journal, 1978