A 0.4 μm 1.4 ns 32b dynamic adder using non-precharge multiplexers and reduced precharge voltage technique

Publisher Website

19 November 2002

proceedings article
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 9-10
https://doi.org/10.1109/vlsic.1995.520663

Abstract

No abstract available

Keywords

This publication has 2 references indexed in Scilit:

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic
IEEE Journal of Solid-State Circuits, 1993
A 200-MHz 64-b dual-issue CMOS microprocessor
IEEE Journal of Solid-State Circuits, 1992