A 28ns CMOS SRAM with bipolar sense amplifiers

1 January 1984

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXVII, 224-225
https://doi.org/10.1109/isscc.1984.1156709

Abstract

This report will discuss a 64K×1 SRAM with bipolar sense amplifiers, utilizing both CMOS and bipolar devices with double poly 1.2μm MoSi processing. The SRAM typically accesses in 28ns and has a 20nA standby mode.

Keywords

RANDOM ACCESS MEMORY
VOLTAGE
CMOS TECHNOLOGY
PROPAGATION DELAY
DELAY LINES
CMOS PROCESS
CIRCUITS
PACKAGING
REGULATORS

This publication has 1 reference indexed in Scilit:

A high-speed, low-power Hi-CMOS 4K static RAM
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1978