On network partitioning algorithm of large-scale CMOS circuits
- 1 January 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems
- Vol. 36 (2) , 294-299
- https://doi.org/10.1109/31.20209
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- Piecewise-linear timing delay modeling for digital CMOS circuitsIEEE Transactions on Circuits and Systems, 1988
- A Survey of Switch-Level AlgorithmsIEEE Design & Test of Computers, 1987
- Macromodeling and Optimization of Digital MOS VLSI CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986