An enhanced high performance combinational fault simulator using two-way parallelism

7 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 294-297
https://doi.org/10.1109/iccd.1989.63375

Abstract

A combinational fault simulator using two-way parallelism and a number of refinements to reduce memory usage is presented. The results show the approach to be generally superior to the basic parallel patterns single fault propagation (PPSFP) algorithm. One of the refinements, processing to encourage the sharing of fault machine indices by independent faults, appears to require substantially more processing time than it saves during simulation. The remaining preprocessing steps are comparable to those used for basic PPSFP, and are highly justified by their run-time savings. The concept of adjusting the parallelism factor to account for increasingly random-resistant faults seems to work quite well.

Keywords

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