A Heuristic Chip-Level Test Generation Algorithm
- 1 January 1986
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 257-262
- https://doi.org/10.1109/dac.1986.1586098
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- Functional fault modeling and simulation for VLSI devicesPublished by Association for Computing Machinery (ACM) ,1985
- Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their TestabilityIEEE Transactions on Computers, 1980
- Test Generation for MicroprocessorsIEEE Transactions on Computers, 1980